As the dimensions of ICs decrease, the thickness of the gate oxide is reduced to maintain performance with the decreased gate length. Conventional gate stacks have become increasingly unsuitable due to uncontrolled fin to fin spacing, breakdown voltage (Vbd) deterioration, and bridge defect as the gate dielectric is thinned proportionally to the decreased gate length.
A need therefore exists for methodology enabling conformal low temperature oxide as a gate oxide for scaled FINFET.